1. Field of the Invention
The present invention relates generally to a system and method for designing integrated circuits or migrating integrated circuit designs from one technology node to another for fabrication by a semiconductor manufacturing process and, more particularly, to a system and method for providing simplified layout processing, for example, optical proximity correction using retarget, for integrated circuit designs to enhance manufacturability and, hence, yield of a semiconductor fabrication process used to produce the integrated circuits.
2. References
U.S. Pat. No. 5,858,580
U.S. Pat. No. 6,430,737 B1
U.S. Pat. No. 6,539,521 B1
U.S. Pat. No. 6,625,801 B1
U.S. Pat. No. 6,792,590 B1
3. Description of the Prior Art
The semiconductor manufacturing industry is continually evolving semiconductor device designs and fabrication processes and developing new processes to produce smaller and smaller geometries of the designs being manufactured, because smaller semiconductor devices typically consume less power, generate less heat, and operate at higher speeds than larger devices. Currently, a single integrated circuit chip may contain over one billion patterns. Consequently, integrated circuit designs and semiconductor fabrication processes are extremely complex, since hundreds of processing steps may be involved. Occurrence of a mistake or small error at any of the design or process steps may necessitate redesign or cause lower yield in the final semiconductor product, where yield may be defined as the number of functional devices produced by the process as compared to the theoretical number of devices that could be produced assuming no bad devices.
Improving time-to-market and yield is a critical problem in the semiconductor manufacturing industry and has a direct economic impact on the semiconductor industry. In particular, a reduced time-to-market and higher yield translate into earlier availability and more devices that may be sold by the manufacturer.
Semiconductor integrated circuit (IC) design and manufacturing processes have become increasingly challenging with each new technology node. With ever decreasing feature sizes, increasing pattern densities, and difficulty experienced in the advancement of IC manufacturing equipment, manufacturing of modern IC designs has encountered substantial impediments and concomitant yield problems within the sub-wavelength regime. Diffraction-limited imaging in the sub-wavelength regime has caused the classical WYSIWYG (“What you see is what you get”) paradigm to disappear. With the emergence of sub-wavelength photolithography, the nonlinearity of the pattern transfer process onto semiconductor material such as silicon has increased dramatically. Due to this phenomenon, the effectiveness of the conventional IC design methodology has been significantly eroded.
In view of the widening gap between design and manufacturability in the sub-wavelength regime, the use of optical resolution enhancement techniques (RET) such as optical proximity correction (OPC) are prevalent in many of the design and manufacturing schema to produce feature sizes of 0.18 μm and smaller. As the feature size decreases, distortion in the pattern transfer process becomes more severe. The design shapes must be modified in order to print the desired images on the wafer. The modifications account for limitations in the optical lithography process. In the case of OPC, modifications of the design image account for optical limitations as well as mask fabrication limitations and resist limitations. Modifications of the design image can also account for the subsequent process steps like dry etching or implantation. It can also account for flare in the optical system, as well as pattern density variations. Another application of proximity effect correction is the compensation of the effects of aberrations of the optical system used to print the image of the mask onto the wafer. In this case, a mask with aberration correction would be dedicated to a given lithography tool as the aberrations are tool-specific.
FIG. 1 illustrates the modification of the mask data to correct for proximity effects. The processing of the mask data starts with a target layout 1 representing the desired dimensions of the image on the wafer. The printed image 2 of the target layout 1 differs from the desired image due to proximity effect. For reference, the target image 1 is shown with the printed image 2. The edges of the features are then moved (3) so that the corresponding printed image on the wafer 4 is correct (as close to the target as possible). In FIG. 1, all the areas of the layout have been corrected, but different degrees of proximity effect correction aggressiveness can be applied to different regions depending on the criticality of the region in the integrated circuit.
The corrections to layout 1 can be applied using a rule-based approach or a model-based approach. For a rule-based approach (rule-based OPC, or ROPC), the displacement of the segments would be set by a list of rules depending, for example, on the feature size and its environment. For a model-based approach (model-based OPC, or MOPC), the printed image on the wafer would be simulated using a model of the pattern transfer process. The correction would be set such that the simulated image matches the desired wafer image. A combination of rule-based OPC and model-based OPC, sometimes referred to as hybrid OPC, can also be used.
In the case of model-based OPC, the original layout 1 as shown in FIG. 2 is dissected into smaller segments 5 shown in modified layout 6. The stitch points of different segments are the dissection points. Each segment is associated with an evaluation point 7. The printed errors of the evaluation points are compensated by moving the corresponding segment in a direction perpendicular to the segment as shown in the final layout 8. The segments are corrected using multiple iterations in order to account for corrections of neighboring segments.
The image quality can be improved by adding printing or non-printing assist features along the edges of the main features. These assist features modify the diffraction spectrum of the pattern in a way that improves the printing of the main feature. The practical implementation of assist features is enhanced with the use of proximity effect correction as described above to correct for any optical printing artifact as well as resist and etch artifacts.
The image quality of an IC design layout can also be improved by another RET known as phase-shifting masks as described in U.S. Pat. No. 5,858,580, for example. In this case, at least two different regions are created on the masks corresponding to different phase and transmission of the light either going through these regions (for transparent mask) or reflected by these regions (for reflective mask). The phase difference between the two regions is chosen to be substantially equal to 180 degrees. The destructive interference between adjacent regions of opposite phase creates a very sharp contrast at the boundary between the regions, thus leading to the printing of small features on the wafer.
Two main classes of phase-shifting masks are currently in use. For the first class, the amount of light transmitted for transparent masks (or reflected for reflective masks) by one region is only a portion of the light transmitted (or reflected) by the other region, typically 5% to 15%. These masks are referred to as attenuated phase-shifting masks or half-tone phase-shifting masks. In some implementations of attenuated phase-shifting masks, some opaque regions (for transparent masks) or non-reflective regions (for reflective masks) are defined on the mask in order to block the light. This type of mask is referred to as a tri-tone mask. For the second class, the light transmitted (for transparent masks) or reflected (for reflective masks) by one region is substantially equal to the light transmitted (for transparent masks) or reflected (for reflective masks) by the other region. The second class of masks includes the following types of phase-shifting masks: alternating aperture phase-shifting masks, chromeless phase-shifting masks, and rim phase-shifting masks. The practical implementation of these techniques is improved with the use of proximity effect correction as described above to correct for any optical printing artifact as well as resist and etch artifacts. All the techniques can be combined with the use of assist features.
Due to design rule constraints or other design decisions, IC design layouts typically have small jogs or other imperfections. Moreover, jogs can be created after design completion with some design rule check (DRC), Boolean or layer operations, or process compensation (e.g., compensation or correction of etch loading effect). The existence of jogs or other imperfections increases the complexity of the original layout in terms of volume of data (e.g., there are more polygon edges, making edge-based operation more complicated), which subsequently complicates the layout processing. For example, as shown in FIG. 2, the typical OPC technique involves a step referred to as “dissection”, or “fragmentation”, in which polygon edges are broken into smaller segments, each of which can be moved independently in order to meet the OPC objective. Most dissection schemes typically force dissection at polygon vertices, which can be undesirable from the OPC perspective.
Considered in more detail, FIG. 3 shows two examples. FIG. 3(a) illustrates a case in which jogs are created due to the swelling of poly lines for contact enclosure. The dominant design rules are a contact enclosure margin and the size of the contact itself. In this example, eight vertices 9 and six edges 10 are created as a consequence of the design rule constraint. Four of the new edges (jogs) 101, 103, 104, and 106 are very small in length, which do not represent true design intent (i.e., it is not possible, and there is no need, to correct the printed image to follow the jog).
The other example shown in FIG. 3(b) illustrates the increase in complexity of layouts due to process bias. Process bias refers to a process applied during part of the lithography process, for example, the etch procedure, in which the patterns are further deformed dependent on a number of factors including the width of the pattern, spacing of the pattern with respect to neighboring patterns, or pattern density in the surrounding neighborhood. These effects need to be compensated, usually by the application of biasing to affected edges in a rule- or model-based fashion before the application of RET). Application of process bias based on neighboring spacing creates jogs on the straight poly line due to neighboring feature spacing variation. As show in FIG. 3(b), four new vertices 9 and two jogs 10 are created.
Existence of jogs or other imperfections generally causes increased complexity and deficiency in OPC, because they do not represent the true intent of design. OPC tools can be configured to apply special treatment to exclude these special cases. However, such an approach typically results in complex and error prone OPC set-up.
One problem that the existence of jogs can cause becomes evident in connection with dissection. The existence of jogs, in the form of a pair of consecutive inner and outer corners, forces dissection at the polygon vertices in a manner similar to dissection of regular corners, as shown in FIG. 4. The difference, however, is that regular corners exhibit corner rounding effects in the printed image, as shown in FIG. 4(b), whereas jogs only cause a small tilt in the printed image whose distortion is far less than the rounding effect. As a result, the control at a jog location is tighter than that at the corners. In many cases, the optimum OPC is achieved by dissecting not at the jog vertices, but by dissecting near them, as shown in FIG. 4(c). This is generally not possible with normal OPC which is forced to dissect at vertices.
Currently, most known OPC techniques apply complicated algorithms to cope with jogs as special cases. This not only causes complexity in OPC, but also may not resolve all cases. This may lead to some jogs that are not considered ahead of time and, hence, not handled properly, which often necessitates rework. This also requires a great deal of flexibility in terms of controlling dissection for the OPC tool itself.
In summary, OPC on real IC design layouts is often handicapped by the existence of nuisance jogs or other imperfections which may be due to design rule or post-design processing such as DRC, process bias, or Boolean operations before OPC is applied. The existence of jogs forces dissection at jog locations which are often not optimal, or simply missing dissection and correction when the jog is too small.
Thus, it would be desirable to provide an IC design layout processing system and method for performing layout processing which overcome the above limitations and disadvantages of conventional layout processing systems and techniques, for example, to solve the difficulty in applying OPC dissection caused by jogs, and facilitate generation of IC designs having improved manufacturability. It would also be desirable to provide a layout processing system and method that are simpler and more comprehensive than conventional systems and techniques currently used by OPC users, which are based on mostly complex algorithms and enumeration of special cases and which are generally more complicated and error prone. Further, it would be desirable to provide a layout processing system and method that can be applied even when the original data have jogs, for example, due to design rules, or are introduced by the application of process bias, for example. It is to these ends that the present invention is directed. The various embodiments of the present invention provide many advantages over conventional IC design methods and systems.